1. Field of the Invention
The present invention relates to polysilicon resistors, and more particularly to a process for fabricating precision polysilicon resistors for use in all integrated circuits. More specifically, the present invention provides a process for fabricating polysilicon resistors in which the tolerances of the sheet resistivity of each resistor across the surface of a single substrate are more precisely controlled.
2. Background of the Invention
Polycrystalline silicon resistors, also called polysilicon or polySi resistors, have been used in the electronic circuit industry for many years. Depending upon their doping and doping levels, p+, n+, p− and n− polysilicon resistors can be fabricated. P+ polysilicon resistors are extremely advantageous for use in analog circuit designs due to their desirable figures of merits. Typically, P+ polysilicon resistors are used in analog and mixed signal circuit designs because they can provide precise matching of subsequent resistors, a low temperature coefficient of resistance, a low voltage coefficient of resistance, and a low parasitic capacitance.
Although polysilicon resistors are widely used in analog circuit designs, such resistors generally have high sheet resistance tolerances ranging from 15–20%. This means the sheet resistance changes by +/−15 to 20%. In current analog and mixed signal applications, and in order to meet stringent circuit performance requirements, circuit designers are demanding lower tolerances in polysilicon resistors.
In the current state of the art, polysilicon resistors are fabricated by ion implanting dopants into a polysilicon layer during the source/drain (S/D) implant step and/or emitter implant step. The implanted dopants in the various regions are then activated utilizing a rapid thermal anneal process. Next, a dielectric layer such as a nitride is applied to the body of the polysilicon resistor so as to protect the body of the polysilicon resistor from being silicided in a subsequent silicidation step. The ends of the polysilicon resistors are then typically exposed and silicided by employing a conventional silicidation process that includes depositing a metal atop the exposed polysilicon end portions and annealing. A single or two-step anneal process may be used in forming the silicide depending on the type of metal that is deposited. The two-step anneal typically includes a silicidation formation anneal and a silicidation transformation anneal.
FIGS. 1A–1D are simple pictorial representations of the above described prior art process of fabricating polysilicon resistors. In these drawings, only a single polysilicon resistor device region is shown. Other device regions including other polysilicon resistor device regions, CMOS (complementary metal oxide semiconductor) device regions and/or bipolar transistor device regions may be formed adjacent to the resistor device region shown. The various device regions are typically isolated from each other by an isolation region, such as a trench isolation region or field oxide region formed in the substrate.
The initial structure shown in FIG. 1A includes semiconductor substrate 10, an optional first dielectric layer 12 located on the upper surface of the semiconductor substrate 10, a polysilicon layer 14 located on either an upper surface of the optional first dielectric layer 12 or an upper surface of the semiconductor substrate 10, and a second dielectric layer 16 located atop the polysilicon layer 14.
In the prior art process, and as shown in FIG. 1A, ions 18 are next implanted into the polysilicon layer 14 within the polysilicon resistor device region through second dielectric layer 16. Note that the ions 18 are also being implanted into other device regions present on the substrate 10. For example, ions 18 may be implanted into the CMOS device regions and/or the bipolar transistor device regions. The implanted ions within the CMOS device regions are used in forming source/drain regions and/or doping of a polysilicon gate conductor, while the ions being implanted into the bipolar device regions are used for doping the polysilicon emitter.
Following this ion implantation step, the dopants within the various device regions are activated using an activation annealing process. FIG. 1B shows the structure after ion implantation and activation annealing. In this figure, reference numeral 14a denotes a doped polysilicon layer.
Next, a protective dielectric 20 is formed atop the second dielectric 16 providing the structure shown in FIG. 1C. Ends of the protective dielectric 20 and second dielectric layer 16 in the resistor device region are removed by lithography and etching to expose a surface portion of the doped polysilicon 14a. The exposed surface portions of the doped polysilicon are then subjected to a silicidation process in which silicide contact regions 22 are formed. The resultant structure including the silicide contact regions 22 is shown, for example, in FIG. 1D.
The above described prior art process of fabricating polysilicon resistors results in undesirable high tolerance resistors having across wafer variations or tolerances in sheet resistance in excess of +/−15–20%. Moreover, in the foregoing described prior art process for fabricating polysilicon resistors, it is generally hard to control the sheet resistance value of the resistors, primarily because of the dopant activation/deactivation and movement in and out of the polysilicon grain boundaries due to subsequent thermal cycles.
In view of the above drawbacks with the prior art process of fabricating polysilicon resistors, particularly the difficulties in controlling the resistance tolerances of polysilicon resistors, there is a need for developing a new and improved process in which precise polysilicon resistors can be fabricated that more precisely controls the tolerances of the sheet resistivity of each polysilicon resistor being fabricated.